An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor-forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using both n-type (negatively doped) silicon that is rich in electrons and p-type (positively doped) silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions to produce the desired concentrations of holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functional, dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS provided a lower-power technology capable of exploiting large scale integration fabrication techniques.
A typical CMOS twin well structure as is commonly used in prior art CMOS memory devices is illustrated in FIG. 1. Specifically, FIG. 1 illustrates a wafer fragment 10 comprising a p-type silicon substrate 12, an NMOS (p-well) memory array region 14, NMOS (p-well) periphery regions 20a and 20b, and PMOS (n-well) periphery regions 22 and 24. During operation of the CMOS memory chip, the n-well regions are biased to the chip supply voltage Vcc, although in some circuit applications certain n-wells are biased to a greater potential Vccp, which is typically twice Vcc and is commonly achieved by a bootstrapping technique. Therefore during operation of the devices fabricated according to FIG. 1, first n-well 24 is biased to Vcc (labelled V.sup.2 cc) and second n-well 22 is biased to Vccp (labelled V.sup.1 cc). P-well regions 14 and 20a/20b are in direct electrical connection with the substrate 12. Such are biased during operation to the desired potential, typically ground and hereafter referred to as Vss, or a slightly negative potential hereafter referred to as Vbb.
A typical method of forming the CMOS twin well structure is to perform a blanket ion implantation of boron (p-type material) over the entire substrate, followed by a photoresist masking step opening the n-well regions, and ion implantation of n-type dopants to form the n-wells. For purposes of the continuing discussion, such defines lateral edges 26 of n-well 22 and lateral edges 28 of n-well 24. Following photoresist stripping, the wafer is then typically subjected to a high temperature "well drive" annealing step which diffuses the implanted n-well and p-well dopants to the desired depths. The process then continues with the fabrication of field oxide isolation regions 15, and fabrication of NMOS and PMOS transistors and other circuit elements. NMOS channel stop implants 13 are provided beneath the field oxide regions in the p-wells, as shown.
Certain aspects of the performance of CMOS memory devices are directly related to the method of fabrication of the CMOS wells as described in FIG. 1, as well as to the bulk substrate properties. For example in a DRAM memory cell typically consisting of an NMOS access device and a capacitor in series, the charge stored on the capacitor upon writing data to the DRAM cell dissipates due to reverse bias leakage of the cell node diode. The length of time over which the DRAM cell can retain a sufficient amount of charge for its intended data state to be determined accurately by a sense amplifier circuit is commonly referred to as "refresh time". Before this period of time expires, the cell must be reprogrammed or "refreshed". It is desirable for the refresh time of a DRAM device to be as long as possible.
This reverse bias diode leakage, which must be controlled to very low levels for acceptable refresh times, consists of two components. A first component is "generation" current due to electron-hole pair generation in the depletion region of the cell node junction. Generation current is very sensitive to the quantity of metallic impurities and crystal defects present in the depletion region of the junction. Extreme care is taken in modern CMOS processing to avoid introduction of metallics and crystal defects, and to trap or "getter" unintentionally introduced impurities at locations away from active regions. "Intrinsic gettering" cycles, wherein oxygen in the silicon substrate is caused to precipitate in the bulk of the silicon wafer to provide sinks for metallics, are often integrated with the CMOS well formation sequence. This is especially true of the well drive step, wherein the oxygen near the surface of the silicon wafer is driven out of the crystal, forming a "denuded zone" in which the devices are fabricated.
A second component of diode leakage is "diffusion" current which occurs by collection of thermally generated minority carriers present in the p-well and substrate which diffuse to the depletion region of the cell node diode. The diffusion length of minority carriers in the silicon substrate can be on the order of hundreds of microns and, since they are thermally generated, their presence in the silicon substrate is unavoidable at normal device operation temperatures of 25-125.degree. C. In modern state-of-the-art DRAM fabrication facilities, where metallic impurity levels are kept at extremely low levels, efforts to improve refresh times are largely focused on reducing this diffusion current component of diode leakage by engineering of the CMOS wells, as will be discussed below.
In addition to thermal generation of carriers in the silicon substrate, very large densities of electron-hole pairs can be generated by the passage of ionizing radiation such as alpha particles through the silicon substrate. One source alpha particles is the decay radioactive impurities such as uranium or thorium, known to be present in trace levels in common semiconductor packaging materials. This alpha-generated charge can be collected by a particular node in a CMOS device, such as DRAM or SRAM memory cell node, in sufficient quantities so as to upset its data state. Such events are termed "soft errors". Soft error rates must be controlled to very low levels for reliable operation of semiconductor devices.
Recently, novel approaches have been taken in CMOS well processing to increase DRAM refresh times and reduce DRAM/SRAM soft error rates by creating barriers to the diffusion of minority carriers from the substrate to the device active regions. In one such prior art technique, commonly referred to as a retrograde p-well structure, boron is implanted into the p-well through an additional mask layer. This is conducted subsequent to the well drive step at relatively high energy to create a buried peak in the p-well doping profile.
FIG. 2 illustrates a cross-sectional schematic 10s of a typical prior art retrograde well structure. In one embodiment of such prior art, a conventional twin well structure as described in FIG. 1 is formed. Later in the CMOS process, e.g. after completion of LOCOS isolation steps, an additional masking step is provided to form the retrograde p-well layer 34 within the p-well regions. Such have lateral edges 23 which do not extend into the n-well regions. Implant 34 is preferably provided as near the p-well surface and at as high a dose as possible without adversely affecting the NMOS device performance. Retrograde p-well layer/region 34 provides a potential barrier to substrate electrons, effectively reflecting them downwardly back into the substrate such that they do not diffuse into the near surface active region and therefore are not collected at active device nodes. Therefore, junction leakage currents are reduced, and thus DRAM refresh times are improved and soft error rates are reduced.
In another technique, commonly referred to as the triple well structure, a buried n-type layer is formed as described with reference to FIG. 3. Similar to FIG. 1, FIG. 3 illustrates a semiconductor wafer fragment 10t comprised of a bulk p-type silicon substrate 12, an NMOS (p-well) memory array region 14, NMOS (p-well) periphery regions 20a and 20b, and PMOS (n-well) periphery regions 22 and 24, all of which are biased in the same manner as described above for FIG. 1. In the triple well structure, wafer fragment 12 is appropriately masked, typically after LOCOS isolation (not shown in FIG. 2), typically with photoresist, and subjected to an ion implantation effective to provide buried n-type electron collector regions 30 to extend into or through n-wells 22 and n-wells 24. Such regions have separated lateral edges 25 and 27 as shown. Accordingly, respective electrical connection of the electron collector regions 30 is provided by the respective extensions into n-well 22 and n-well 24 as defined by the masking layer used to produce regions 30. The n-type buried regions 30 provides soft error protection and increases DRAM data retention time by collecting stray electrons from the substrate that might otherwise be collected by device active regions.
The masking provided to facilitate production of buried layer/regions 30 leaves all or part of the array portion of p-well region 20b uncovered, but does cover all or part of p-well region 20a to assure that the illustrated two electron collector regions 30 do not connect with one another or short the two different n-wells 22 and 24, which are normally biased at different voltages.
The implant ions utilized to produce layer/regions 30 are typically phosphorus. Although the effectiveness of regions 30 in collecting substrate electrons increases with the phosphorus implant dose, the dose is limited in practice to control its final vertical width such that it does not electrically affect the device active region at the wafer surface. This practical dose limit is dependent on subsequent thermal processing during which diffusive broadening of the phosphorus profile occurs.
It would be desirable to develop methods which facilitate formation of CMOS circuitry within a semiconductor substrate having features to contend with substrate diffusion currents and alpha particle ingestion, and preferably which minimize masking steps.